SDRAM Technology's blog
Submitted by SDRAM Technology on Sun, 05/30/2010 - 19:53
MOS = Metal Oxide Semiconductor
RAM = Random Access Memory
DRAM = Dynamic Random Access Memory
SDRAM = Synchronised Dynamic Random Access Memory
FERAM = Ferroelectric Random Access Memory
MRAM = Magnetoresistive Random Access Memory
PRAM = Phase-change Random Access Memory
VRAM = Video Random Access Memory
WRAM = Window Random Access Memory
Submitted by SDRAM Technology on Sat, 02/27/2010 - 23:41
It is not a seecret that micrtoelectronic chips are fabricated in "clean rooms". The reason for this is very simply: to avoid defects which could compromise the functionality of the chips.
However, what is a defect? That’s a simple question, but very difficult to answer!
Submitted by SDRAM Technology on Fri, 10/16/2009 - 15:45
What is actually a “bank”. In the DRAM world the notion “bank” has three different meanings:
- there are internal banks on the chip as discussed in the article ….
- the term "bank" is also sometimes used for the individual memory slots in a computer
- and finally there are also the “banks” of a DRAM module, this is what we are going to discuss in the following.
Submitted by SDRAM Technology on Thu, 10/15/2009 - 09:37
Modern desktop processors operate with a 64-bits bus. However, some SDRAM DIMMs are 72-bit wide, why? Additional 8-bit are called “parity bits”, or "parity byte". The parity bits offer the computer the possibility for error detection and correction. In order to realize this useful feature during the write procedure, for each byte of the bus (64 bits = 8 x 8 bits, i.e. the bus is 8 bytes wide) the so called checksum is build and stored in a single parity bit. Thus, for a 64-bit wide bus 8-parity-bits are needed.
Submitted by SDRAM Technology on Mon, 10/12/2009 - 11:14
"PCBs" is the abbreviation for "Printed Circuit Board" and is actually the board on which the whole module is built. For standard DIMMs the PCB is an epoxy resin that is dyed green and consists of several (e.g., four) insulating layers which are separating the conductive layers (consisting of copper) from each other. The individual copper conductive layers are connected with each other through contact holes, also called "VIA's. From several conductive layers only some of them are made of structured conducting paths, e.g. the front and posterior outer layer (these conducting paths are then visible) and the middle layer. Between the layers with structured conducting paths, two continuous/bulk (without structured conducting paths) conducting layers are present, one of them being connected to the power supply VCC and the other one is connected to ground. By means of these two continuous copper layers a good distribution of the supply voltage over the entire module is provided and in addition they are playing the role of capacities (charge reservoirs) able to “catch” undesired big current peaks. The DIMM pins are usually made of gold, deposited on the boards by means of electroplating.
Submitted by SDRAM Technology on Thu, 10/08/2009 - 11:54
The threshold voltage (Ut) of a Field Effect Transistor (FET) is the voltage applied on the gate of the transistor at which a measurable current between source (S) and drain (D) is starting to flow. At this voltage an inversion layer under the gate (between source and drain) is formed, so that the pn-junctions (immediately under the gate) are vanishing and thus a current path between drain and source is obtained. The resistance of these this current path (inversion layer) depends on the thickness of the layer, which is determined by the applied gate voltage. A schematic overview of measurement setups for threshold voltages of N-FET and P-FET transistors is presented in Figures 1 and 2.
Submitted by SDRAM Technology on Fri, 10/02/2009 - 09:37
A leakage current is the current which is flowing thought a pn-junction when is inversely polarized. As the definition says in order to measure the leakage current of a pn-junction you simply have to apply a voltage in the reverse direction of the junction and measure the resulting current. A schematic picture of this process is presented in Figure 1.
Submitted by SDRAM Technology on Wed, 09/30/2009 - 18:11
A SDRAM chip contains a lot of structures like pn-junctions (diodes), transistors, resistors, P/N-walls etc. In order for a chip to function well the structures enumerated before should fulfill some criteria specified by the designers of the chip. Thus, methods are needed to measure the properties of “transistor & Co” in order to see if the manufactured structures fulfill the specified criteria.
Submitted by SDRAM Technology on Sun, 09/27/2009 - 18:27
The semiconductor device reliability is defined as a degree or characteristics that indicates the functional stability of the device over a time. The degree of reliability is the probability in that the device executes its defined functions during an estimated period under defined conditions. In general, the failure rate at time 0 is expressed as part per million (ppm). The failure rate during the periods of initial and random failures is expressed as Failure in time (Fit), where 1 Fit=10-9/time. The wear-out failure period is expressed as Time To Failure (TTF), which refers to the life until a certain cumulative failure rate is reached.
Submitted by SDRAM Technology on Wed, 09/23/2009 - 10:24
Let us assume that we want to access the memory cell which is situated at the intersection of WL2 and BL3 in an SDRAM array-segment (see Figure 1 for illustrations). WL2 and BL3 are the word-line number two (2) and bit-line number three (3) correspondingly. See the article “What are bit-lines and word-lines on a SDRAM chip?” for more details about bit-lines and word-lines.