Submitted by SDRAM Technology on Tue, 09/01/2009 - 23:12
As discussed in “SDRAM Chip Architecture / Structure: Array and Periphery” article the smallest memory-array unit of a SDRAM chip is the array-segment. An array-segment is a two dimensional array consisting normally of 512 x 512 bits, or can be bigger depending on the used technology (see Figure 1). As with any array in order to access one of its elements, in our case a memory cell, you have to specify the raw-number and column-number. The intersection point of the specified row-column pair will be the addressed element (Figure 1).
Submitted by SDRAM Technology on Tue, 08/18/2009 - 14:45
SDRAM chip design is varying strongly from company to company, technology node to technology node and can also depend on the chip capacity (512 Mb, 1Gb, 2Gb etc.). The architecture is defined by the chip designers taking into account the particularities of the designed chip (see Figure 1 and 2). However, independent from the factors named above a SDRAM chip can be divided in two main parts:
Submitted by SDRAM Technology on Mon, 08/10/2009 - 13:35
As already mentioned in the article SDRAM elementary cell, the DRAM components (i.e. the transistor and the capacitor) are not ideal and the information (charge) can leak from/into the capacitor and destroy the information inside the DRAM cell. Charge leakage occurs mainly due to imperfection of the capacitor and of the p-n-junctions making the transistor (source and drain). A schematic representation of how the charge can leak is presented in Figures 1 and 2. As a result of charge leakage the DRAM memory cells have to be often refreshed in order to avoid loosing information. Due to this refreshing procedure the DRAM is called Dynamic RAM (random access memory), i.e. the charge can not stay in the capacitor forever and should be dynamically refreshed.
Submitted by SDRAM Technology on Fri, 08/07/2009 - 12:23
A FOUP (Front Opening Unified Pod) is a closed and transportation safe box for wafers within a semiconductor factory. The main purpose of a FOUP is to isolate the wafers from the clean room environment. The FOUP concept allows to save investments needed for a class 1 clean room. Due to the fact that inside the FOUP a special microclimate/micro-clean-room is generated/maintained and the wafers are isolated from the clean room atmosphere, the class of the clean room itself can be higher(=worse), e.g. 1000, as would be necessary without the FOUP concept. Investments and maintenance for a class 1000 clean room are much lower as compared with a class 1 clean room. Due to this reasons, FOUPs are indispensable accessories in modern 300mm microelectronic factories. Examples of FOUPs can be seen in Figure 1 and 2.
Submitted by SDRAM Technology on Tue, 07/28/2009 - 10:20
The SDRAM chips are manufactured on silicon wafers. Depending on the size of the chips and the size of the wafer a different number of chips can fit on one wafer. The state of the art wafers in microelectronics are at the moment (year 2009) the so called “300 mm wafers”, which certainly means that the diameter of the wafer is 300 mm. Depending on the technology node (90nm, 70nm, 60nm etc.) and the bit capacity of a SDRAM chip (512 Mb, 1Gb, 2Gb or even 4 Gb) the number of chips which can fit on one wafer can vary strongly. A typical SDRAM chips size is 30-50 mm2 and thus on a 300mm wafer can fit more that 1000 chips. A relatively high number taking into account that a normal SDRAM DIMM or SODIMM module needs 8, 16, 32 etc chips to be build.
Submitted by SDRAM Technology on Mon, 07/20/2009 - 23:00
For synchronous DRAM (SDRAM) unbuffered, registered and stacked modules are usual. In the following I will explain what registered and stacked modules are:
Submitted by SDRAM Technology on Sun, 07/19/2009 - 21:38
For non-synchronous DRAM, like EDO/FPM, buffered and unbuffered modules were usual. What is the difference actually between unbuffered and buffered DRAM modules?
Submitted by SDRAM Technology on Sun, 07/19/2009 - 15:31
In one of the last articles I discussed the purpose of the Back End Test, in this article I will shortly describe what are the stages of a Back End Test. A Back End Test is done on the chipe level and can have the following test stages (see also Figure 1):
Submitted by SDRAM Technology on Sat, 07/18/2009 - 22:45
Submitted by SDRAM Technology on Sat, 07/18/2009 - 17:53
The input for Chip Level Assemby are the wafers coming from a Front End Factory (FE). In order to cut the wafers in separated chips the following steps are usual but can vary slightly from company to company: