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MOS Memory Tree

MOS Memory Tree


MOS = Metal Oxide Semiconductor

RAM = Random Access Memory

DRAM = Dynamic Random Access Memory

SDRAM = Synchronised Dynamic Random Access Memory

FERAM = Ferroelectric Random Access Memory

MRAM = Magnetoresistive Random Access Memory

PRAM = Phase-change Random Access Memory

VRAM = Video Random Access Memory

WRAM = Window Random Access Memory

What is semiconductor reliability?

The semiconductor device reliability is defined as a degree or characteristics that indicates the functional stability of the device over a time. The degree of reliability is the probability in that the device executes its defined functions during an estimated period under defined conditions. In general, the failure rate at time 0 is expressed as part per million (ppm). The failure rate during the periods of initial and random failures is expressed as Failure in time (Fit), where 1 Fit=10-9/time. The wear-out failure period is expressed as Time To Failure (TTF), which refers to the life until a certain cumulative failure rate is reached.

SDRAM Write-Read basics

Let us assume that we want to access the memory cell which is situated at the intersection of WL2 and BL3 in an SDRAM array-segment (see Figure 1 for illustrations). WL2 and BL3 are the word-line number two (2) and bit-line number three (3) correspondingly. See the article “What are bit-lines and word-lines on a SDRAM chip?” for more details about bit-lines and word-lines.

What are bit-lines and word-lines on a SDRAM chip?

As discussed in “SDRAM Chip Architecture / Structure: Array and Periphery” article the smallest memory-array unit of a SDRAM chip is the array-segment. An array-segment is a two dimensional array consisting normally of 512 x 512 bits, or can be bigger depending on the used technology (see Figure 1). As with any array in order to access one of its elements, in our case a memory cell, you have to specify the raw-number and column-number. The intersection point of the specified row-column pair will be the addressed element (Figure 1).

SDRAM Chip Architecture / Structure: Array and Periphery

SDRAM chip design is varying strongly from company to company, technology node to technology node and can also depend on the chip capacity (512 Mb, 1Gb, 2Gb etc.). The architecture is defined by the chip designers taking into account the particularities of the designed chip (see Figure 1 and 2). However, independent from the factors named above a SDRAM chip can be divided in two main parts:

Chip Level Assembly

The input for Chip Level Assemby are the wafers coming from a Front End Factory (FE). In order to cut the wafers in separated chips the following steps are usual but can vary slightly from company to company:

SDRAM elementary cell

As shown in Figure 1 a SDRAM elementary cell has two main parts:

  1. a transistor;
  2. and a capacitor;

The transistor plays the role of a switch and the capacitor is a place to store electrical charge. In order to store a physical “1” in a SDRAM cell the following processes take place:

  • Transistor opens
  • The charges/electrons are flowing and fill the capacitor
  • The transistor closes

SDRAM Abbreviations

A list of most common abareviations used for SDRAM:

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