What is SDRAM parity?
Submitted by SDRAM Technology on Thu, 10/15/2009 - 09:37
Modern desktop processors operate with a 64-bits bus. However, some SDRAM DIMMs are 72-bit wide, why? Additional 8-bit are called “parity bits”, or "parity byte". The parity bits offer the computer the possibility for error detection and correction. In order to realize this useful feature during the write procedure, for each byte of the bus (64 bits = 8 x 8 bits, i.e. the bus is 8 bytes wide) the so called checksum is build and stored in a single parity bit. Thus, for a 64-bit wide bus 8-parity-bits are needed.
Figure 1: Examples of SDRAM modules with and withoput parity-chips
On the other hand, during the reading process the checksums are build again using the content of the read bytes and these new checksums are checked against the old checksums stored during the write process. Is the new and old checksums do not coincide the computer will receive an error code (EC-mode: Error Code). This error code can be intercepted and therefore the crash of the computer will be avoided. More than that, there is even the possibility of using the parity bits in order to correct the error and thus to avoid the error pup up on user interface (ECC mode: Error Correction Code).
Unbuffered Modules can be found both with and without parity byte. For the unbuffered modules using 8 chips/side an additional chip/side should be build in order to provide the parity-functionality. Thus, such a module will have build 8 chips/side without parity and 9 chips/side with parity (see Figure 1).